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SN54/74LS490 DUAL DECADE COUNTER
The SN54 / 74LS490 contains a pair of high-speed 4-stage ripple counters. Each half of the SN54 / 74LS490 has individual Clock, Master Reset and Master Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code.
* * * *
Dual Version of SN54 / 74LS490 Individual Asynchronous Clear and Preset to 9 for Each Counter Count Frequency -- Typically 65 MHz Input Clamp Diodes Limit High-Speed Termination Effects
DUAL DECADE COUNTER
LOW POWER SCHOTTKY
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 CPb 15 MRb 14 Q0b 13 MSb 12 Q1b 11 Q2b 10 Q3b 9
16 1
J SUFFIX CERAMIC CASE 620-09
1 CPa
2 MRa
3 Q0a
4 MSa
5 Q1a
6 Q2a
8 7 Q3a GND
16 1
N SUFFIX PLASTIC CASE 648-08
PIN NAMES
LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 1.5 U.L. 5 (2.5) U.L.
16 1
MS MR CP Q0 - Q3
Master Set (Set to 9) Input Master Reset Clock Input (Active LOW Going Edge) Counter Outputs (Note b)
0.5 U.L. 0.5 U.L. 1.5 U.L. 10 U.L.
D SUFFIX SOIC CASE 751B-03
NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.
ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC
LOGIC DIAGRAM (ONE HALF SHOWN)
MS 4 12
TRUTH TABLE
OUTPUTS COUNT 0 1 2 Q3 L L L L L L L L H H Q2 L L L L H H H H L L Q1 L L H H L L H H L L Q0 L H L H L H L H L H
CP
1 15 K CD 2 J SD Q K CD J Q K CD J Q K CP J CD SD Q
3 4 5 6 7 8 9
MR
14
3 Q0 13
5 Q1 11
6 Q2 10
7 Q3 9
FAST AND LS TTL DATA 5-1
SN54 / 74LS490
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 MS, MR IIL IOS ICC Input LOW Current Clock Short Circuit Current (Note 1) Power Supply Current - 20 -1.6 - 100 26 mA mA - 0.4 mA VCC = MAX VIN = 0 4 V MAX, 0.4 VCC = MAX VCC = MAX 0.35 0.5 20 IIH V A mA 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH , , or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table
VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC SET-UP REQUIREMENTS (TA = 25C, VCC = 5.0 V)
Limits Symbol S bl tW ts Parameter P Any Pulse Width MR or MS to Setup Time Min 20 25 Typ Max Unit Ui ns ns VCC = 5 0 V 5.0 Test C di i T Conditions
FAST AND LS TTL DATA 5-2
SN54/74LS490
AC CHARACTERISTICS (TA = 25C)
Limits Symbol S bl fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL Parameter P Maximum Clock Frequency Propagation Delay, CP to Q0 Propagation Delay, CP to Q1 or Q3 Propagation Delay, CP to Q2 Propagation Delay, MR to Output Propagation Delay, MS to Output Min 25 Typ 35 12 13 24 26 32 36 24 24 20 20 20 39 39 54 54 39 39 36 Max Unit Ui MHz ns ns ns ns ns Figure 1 Figure 1 Figure 3 Figure 2 Figure 2 Figure 2 VCC = 5.0 V, 5 0 V, CL = 15 pF Test C di i T Conditions
AC WAVEFORMS
*CP
1.3 V tPHL tW 1.3 V
1.3 V tPLH 1.3 V
Q
Figure 1
MR & MS
1.3 V tW
1.3 V trec 1.3 V
CP tPHL Q 1.3 V
Figure 2
MS
1.3 V tW
1.3 V trec 1.3 V
CP tPLH QO, Q3 1.3 V
Figure 3
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the Truth Table.
FAST AND LS TTL DATA 5-3

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